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  • In one of the previous videos I

  • talked about this multi-level cell or MLC technology.

  • And I described to you how cool of a technology it was.

  • That it essentially allowed me to store twice or thrice or

  • sometimes even four times the amount of data in the same cell.

  • So it was clearly a technology meant for

  • tough economic times or you know times of recession,

  • but I, what I want to do in this video is to talk a little bit about

  • what is the trade off?

  • What is the trade off if I store two or three or four bits per cell.

  • So how does the performance change as compared to,

  • you know, storing a single level in the cell?

  • And to do that I need to introduce two new terms in your vocabulary.

  • One is called the endurance or or also called as cycling, and the other

  • term I want to introduced is stress induced leakage current, also called SILC.

  • So let's look at what these terms mean first.

  • So the first term I want to introduce is called endurance.

  • it's also sometimes called cycling, and cycling here

  • has

  • you know little relationship with what Lance Armstrong used to do.

  • But, what cycling a cell or endurance of a cell, is, means is that, it's,

  • each time you program or erase the cell,

  • each of that operation is called, cycling operation.

  • And typically for these single-level cells you have up to 10 to power five.

  • They're meant to, you know,

  • last up to 10 to power five cycle.

  • Or you can program or erase them 10 to power five times.

  • So what do I mean by this endurance or these, cycling?

  • So what happens when you a programmer, erase these cells

  • And you inject these electrons out of the cell when you want to erase it.

  • So you are flowing these electrons in and out, using,

  • you know, by doing this program/erase operation in the cell.

  • And what happens is that it degrades the quality of this tunnel oxide.

  • So remember

  • these tunnel oxide as well as these inter-poly dielectric or IPD oxide.

  • These are insulator materials.

  • Silicon oxide, or, you know, similar dielectric materials.

  • And what we're doing here is we are essentially

  • flowing current in and out of these tunnel oxide.

  • So we are treating them, as conductors when they are really insulated.

  • So these material don't tend to like that, and

  • what happens is that over a period of time when

  • you keep on programming and erasing the cell when you.

  • you are essentially flowing electrons in and you are flowing electrons out.

  • Some of these electrons get trapped in this tunnel oxide.

  • And what that does is that it it changes your

  • programmer/erase window so now you have some electrons already trapped in

  • your tunnel oxide.

  • So your VT or your threshold voltage of your erased state is essentially

  • goes up because there's already several of trap charge stored in your cell.

  • At the same time these electrons, they prevent these, these electrons which are

  • trapped in your oxide, they prevent other

  • electrons from flowing into your floating gates.

  • So, you are, you are able to store less number of electron in your program state.

  • So your program VT degrades, so your

  • program VT essentially degrades or it, decreases.

  • And your erase VT increases.

  • So in turn what happens, is your program/erase window which is the determined by

  • this difference between my program. And erase state that window starts to close.

  • Or this window is essentially, it's decreasing.

  • And so these typically these, cells are build such that they can

  • survive this program, erase cycling to up to 10 to power five cycles.

  • Or they are meant to endure this program erase operation.

  • To up to 10 to the power of five times. The other term or

  • you know the other phenomena which happens when you program and erase these cells is

  • a stress induced leakage current, which starts to happen.

  • It's also known as SILC, standing for stress induced leakage, current.

  • So what it means is that when I keep

  • on programming and erasing my cells, I'm stressing these tunnel

  • oxide materials because, you know, they are not really meant to be conductors.

  • And when you are flowing electrons in and

  • out, you are essentially stressing them and you,

  • they don't like it so what happens is

  • that these trapped states are developed in my dielectric.

  • So it creates these trap states in my insulator material.

  • And it's you know, it's not as

  • bad if there's, there's only one of these trapped states.

  • But these trapped states when they line up in this manner as shown over here.

  • So they can what they can do is they can allow tunneling of electrons

  • through these trap states, so these trap states can assist the tunneling

  • of electrons from my silicon into my floating gate.

  • Also

  • from my floating gate back to my silicon. And this especially

  • plays a lot of havoc at low voltage state because ideally if I was in

  • a, if I was applying a low voltage between my silicon and my floating gate.

  • I would expect a little or no tunneling but

  • because of these trap states which build up due

  • to cycling of my device and the stress which comes with my cycling.

  • Instead of getting zero current, so I now get a

  • substantial current at these low voltage at across my dielectric.

  • And this phenomenon is known Stress Induced Leakage Current.

  • So this was the ideal case where you know, from a theoretical, from our

  • or direct tunneling model you would expect, you

  • know negligible current less than a Picoamp of current

  • but because of these stress induced leakage.

  • All these traps states, you get this high

  • amount of or you get this tunneling current.

  • And this tends to again also degrade degrade the performance of your cells.

  • So suppose you had a retention requirement of 10 years and you

  • had a lot of these trap states created during programming or

  • erasing your cell.

  • Your charge can now leak out, you know in less than a year.

  • So now that we know about endurance and, cell

  • , let's look at what happens to the

  • distribution of, threshold voltages as we cycle our cells.

  • So in one of the previous videos that I talked, you know, that our threshold

  • voltage, it has this Gaussian kind of distribution for each of

  • this state, so this is my state zero, this is maybe my state one, two, and three.

  • So it has, when I initially program

  • this cell, it has this tight distribution around a narrow,

  • set of threshold voltages, but what happens as I cycle my cells?

  • So let's say this was my state you know, at my very first time I program or

  • cell.

  • so when I cycle this cell, after, let's

  • say, 1000 cycles, this distribution becomes more wider.

  • So it becomes maybe let's say after 1,000

  • number of cycle it becomes something like this.

  • When I have a larger range of my threshold voltages because as I

  • talked about you know, I'll be building up some charge so it will

  • degrade my erase VT and you know increase you know, degrade, increase

  • my erase VT and degrade my program VT so as a result.

  • On a statistically speaking, I'll get a larger threshold voltage distribution.

  • And as I keep on going even further, maybe you know, I'll get an even

  • larger distribution when I'm programming it 100k times 10 to power of

  • five times.

  • So or, as I keep on cycling myself there's a distribution of threshold voltages.

  • For one particular state it keeps on increasing.

  • And this was, this have been fine if I had, you know, just two states and had a

  • very large separation between these states but as you can see if if I have four

  • of these states.

  • When I when I, you know, keep on cycling them,

  • each of these states will, you know, expand in its distribution.

  • And if these distributions starts you know, coinciding

  • with each other, then I have a problem.

  • And if this was a problem, if you think this was a problem in a two

  • bit per cell, let's look at, you know, if I had three bits per cell.

  • So if I was storing three

  • of these bits file.

  • We be having, two to power three of these are eight of these states.

  • And now each of these states, as I keep

  • on, cycling them, they will set each of them will, will

  • have, you know, this is very first time

  • I program or erase them and then this is maybe after.

  • thousand times and this is after

  • ten to power five time.

  • So you know, you can can clearly see that if I if I program three bits

  • per cell or a TLC cell for ten to power five times, I'll

  • be getting these overlapping regions which I don't know which state my cell is.

  • Whether it's in slate three or whether it's in state four.

  • So one of the major limitation you get

  • when you store multiple levels in one single cell is that you can.

  • Only program and erase them for let's say 10 to power

  • four, or 10k cycles, or 10 to power three times, or 1k cycles.

  • And this is summarized in this table over here.

  • So as you can see here, if I had a single level cell at a you know at 50

  • nanometer technology or even at a 30 nanometer technology,

  • I could cycle it 10 to the power five or 100 k times.

  • And I could still distinguish between these two, to my program.

  • And it is state which had very large seperation between them.

  • But now, let's I have MLC cell with two bits

  • stored per cell. So I have these states very close to each other, and I can

  • only program and erase it in this case you know 10K times.

  • And again this degrades as I keep on scaling myself, if I have if I go

  • to a 30 nano-meter technology that leaves me only with even

  • fewer electrons and then I can program and erase this cell only 5k times.

  • And if I go to a 20 nanometer technology this number is 3k times.

  • So and if I have, even if I store three bits per cell or if you know, if I have

  • if I have that means you know, two to power three or eight levels in my cell.

  • I can, you can see, I can only program

  • and erase it over 2500 times and you know, it's less

  • than a 1000 times if I go to a 20 nanometer technology.

  • So this is you know one of the main main Bottlenecks or one of the main

  • trade-offs that if you have a multi-level cell, if you

  • can see over hear that, if you go from a single-level cell You could program it

  • a 100k times.

  • versus if you go to 50 nanometer MLC cell, you can program it only 10 k times.

  • And if you scale your scale, if it's a 20

  • nanometer technology, you can program and erase it only 3,000 times.

  • And to you know, to, to kind of, you know mitigate the impact of this.

  • What you do is you increase the number of error correction, code.

  • So you store these extra bits which, correct for

  • the state of the cell in case something goes wrong.

  • And you really didn't want to lose data, so you.

  • introduce this ECC error correction a, you know, a bits.

  • And these are the number of bits that you have to introduce, which is essentially

  • a penalty on your overall chip performance that keeps on increasing.

  • So your ECC requirement it again keeps on increasing if you store multiple

  • bits per cell. There are other trade-offs as well

  • So, if you store a multiple of these levels

  • in one cell, you have to read, or you

  • have to, you know, essentially distinguish between this multiple

  • of these levels here or even to read one

  • of these cells, you essentially need to distinguish, earlier you just had to

  • distinguish between two levels, now you have

  • to distinguish between four or eight levels.

  • So if you're doing a random read, you know

  • your controller takes some time to figure out, you know,

  • what state your cell was, so your, so if you're

  • doing a random read, your read, time increases as well.

  • So, as we start to

  • summarize, you know, we, to compare my MLC versus single level cell technology.

  • my MLC certainly has the advantage that you know,

  • it can it can, it's very economically viable cell

  • it can let me store you know twice or

  • thrice or four times the data on the same chip.

  • But, on the other hand it comes with these

  • trade offs that you know, I, my number of cycles that I can program or erase

  • it degrades from, you know, 10,ah, 100k, to, as we saw,

  • less than 10k for, you know, a two bits per cell, and, you know, even less

  • than 100, less than 1k for, for a triple level cell.

  • at the same time it's slower to read

  • so that's another trade-off.

  • So all in all it comes, you know it's a mixed bag of results, you

  • do gain in capacity but it comes

  • with the MLC technology comes with these trade-offs.

In one of the previous videos I

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B1 erase program cycling oxide state nanometer

MLC NAND Flash: More with less: tradeoff

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    陳震寰 posted on 2015/05/01
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