the full name is microelectromechanical systems and this is a very emerging area today and

lot of work is going on around the globe on MEMS and Microsystems and it has got enormous

applications. Today, we will highlight the basic applications and some of the introduction

on MEMS and Microsystems.

Now, the MEMS topic or microsystems is an offshoot of the microelectronics and so to

start the course on MEMS and Microsystems, we will start from microelectronics and let

us look back little bit into the back of the present MEMS which is microelectronics and

we will look into the history on microelectronics.

So, this particular figure you can see the three scientists who are the Bardeen, Brattain

and Schokly from the Bell Laboratories and you know these three scientists first discovered

the Point Contact Transistor which is in 1947. For that discovery they got Nobel Prize in

1956 and that was the first time Nobel Prize was awarded for an engineering device. You

know Nobel Prize is not given for any engineering branch. It is given on basic science, physics,

chemistry, mathematics, and etcetera. But here the Nobel Prize was given in physics

for engineering device.

Later on these three scientists developed a technique by which silicon can be oxidized

and oxidation demonstrated by them in 1953 at Bell Lab. Because of that demonstration

of oxidation from silicon, basically the people started thinking why we cannot make the transistor

on silicon monolithically. The first invention on transistor was a point contact that is

a diskette. Basically, they combined three pieces of silicon N P N and something like

that and then they took contact on each point and they got the transistor action.

This figure you can see is Jack Kilby and he invented integrated circuit in 1958.You can see here so that is the US patent and

which was submitted in February 6, 1959 and this was in September 1958 the patent was

written and that was the first monolithic integrated circuit you can see the picture

here and this gentleman is Jack Kilby and he got again Nobel prize for this particular

device in the year 2000.

So, from that time onwards people are not seeing back and they are proceeding forward,

particularly in the context of miniaturization of different components and making the integrated

circuits. Now this picture you see is the MOS transistor which contains over one million

MOS transistors and that is in early 1990s. Now if you look back to compare the revolution

in the integration of the components, we have to go back to the first transistor which is

also monolithic and that was made in 1960s, where four BJTs and several resistors are

connected together with some metal line. You can see this is a metal contact, this is a

metal born pad, here is another metal born pad and the four transistors and several resistances

were integrated to get some functions off to get some circuit.

Now, after that if we see the what is the status and the what are the trends of silicon

ICs, we have to see this particular figure where this has been obtained from CR route

map and here in one side you can see the minimum feature size of the transistor starting from

1970 to 2020 and on the other side you can see the number of transistors for DRAM chip.

So now look at this figure, here in 1980 where these minimum feature sizes was nearly say

2000 nanometer and then if you go, at present this is the present line 2004 and there you

can see the feature size is nearly 100 nanometer.

So, on the other side, the DRAM chip which is basically always cited the integration

level and that integration level starts from the 4 Kilobyte this is the nineteen four kilobit

DRAM which has come in 1970 and later on you can see from 4 Kilobyte to 64 Kilobyte then

1 Megabyte to16 Megabyte and so on. At present 256 Megabyte DRAM, where this is nearly in

1998 or 99 it came and there transistor count you can see here is one 10 to the power 9

so that means is nearly people are thinking at the moment so transistor level has come

of the order of 10 to the power 10 transistors for DRAM chip.

Now, if you here is one limit by 2010 and 2012, we can see the number of neurons in

the human brain in 15 centimeters cube is nearly 10 to the power 11. 11 is the total

number of the neuron cells and people are speculating that, by that time the number

of transistors for IC or DRAM chip will achieve in that level.

So now, this is another picture you can see which is basically Moore's Law and that gives

you the scaling of the CMOS. That means year to year how the integration is taking place,

you can see from here the model CMOS in 1980 which is nearly one micron technology and

then at present in 2004, the transistor size has come down to 19 nanometer only. Here basically

a route map is given by an international organization and that is the semiconductor route map they

call it, and in the last 34 years the scaling history is such that every generation feature

size sinks by 70 percent.

What do you mean by the generation? The generation basically, on an average of every 2.9 years

they speculate something, they foresee something and after that on that particular year again

depending on the progress of the design and progress of the technology they again just

to control something so the next two years what will happen, so that is basically the

route map. Earlier this generation is nearly 2.9 years but later on the progress is so

fast that has been changed to 2 years recently every two year they are speculating something.

Before that time target achieved, they got something else, much more progress has been

done.

Now, basically the scaling of the CMOS if you can see that the beginning of the some

micron era is started nearly say mid of 85, a mid of 80s that is 1985 nearly in that after

that deep UV lithography then 19 nanometer in 2004. So if you continue in this fashion

so reasonably by 2020, they will come to a limit and that limit of scaling, that means

there the problem is the lithography alignment or which will be the source of lithography.

So, optical lithography is a commercial technique, you know after they highlight, they proceed

to UV, deep UV and then after deep UV there are certain other lithography techniques which

are basically x-ray or lithography but those are not commercially viable.

The people want to stick on optical lithography itself so that's why optical lithography create

some problem after the 90s nanometer and below. Lot of intervention and techniques people

are using in the optical lithography so that they can get the feature size below these

90 or now at present 60 or 65 nanometer people are working on.

But now the silicon microelectronics basically if you see, that is the silicon wafer is 1

0 0 crystal orientation wafer. Now, at present the standard size of the silicon wafer in

industry is nearly 12 inches. Normally in some cases the 4 inch or 6 inch and 8 inch

wafers are also used in some of the small fabs but in big fabs they are working on 8

to 12 inches. Now, you know the lots of circuits are made on silicon wafer and individual single

chip and that is of the order of 2 centimeter square.

I am talking about a larger chip size which you can make now days, is of the order of

2 centimeter square that does not mean that feature size is also very large. Feature size

is very small and if you can get the larger die side that is another achievement. Feature

size goes down and this is known as the die and the die size goes up so that is the challenge

of the technology. Now currently what I just mentioned few minutes back, that the number

of transistors per chip has exceeded the 1000 million. So this is heading towards the billion

and projection in 2014 is 20 billion transistors per chip and that is

the projection at the moment.

Now, here is another diagram, where you can see the feature size goes down, so if you

look into the integrated circuit history, below this is a 0.1 micrometer and this is

10 nanometer range, this is the one transition 0.1 to 10 nanometer and then another transition

level is 10 nanometer to 1 nanometer. So 1 nanometer means this transition is very important

to people and is basically the quantum devices. Now you know the lattice, the constant of

silicon is nearly 3 or 4 or 5 nanometer. Now if you go into 10 nanometer that means few

2 or 3 the atomic diameter is like that. So, that means the few monolayers of silicon within

that if you go into this region then you have to make the devices.

So there, the normal physics of the transistor may not be valid and you have to go into the

quantum mechanical analysis and those are basically the quantum devices. Below that

are atomic dimension and the automatic atomic dimension level, when you make the transistor

lot of other problems will come into the picture. Then here is another table which shows that

the trend of the feature size as well as the wiring levels the mask count and supply voltage

that all this figure tells that is in 1997 where the supply voltage is nearly 2 volts

and in 2003 it is 1.2 volts and people are looking for the circuits and devices which

will work in the 1 volt and at 2012 it's a 0.5 to 0.6 volt.

So, you see how the feature size goes down and at the same time the chip size is going

up as just now I mentioned to 80 millimeter square so they are speculating in 2012 it

will be 1580 millimeter square. The number of transistors in that regime is 1.4 billion

and that is wiring level. That means in the present all the microprocessor chips, the

seven or eight level of metallization is being done there. You know if the number of levels

is more the technology is getting much more complicated and obviously the yield is another

important point which is another yardstick. So, how your technology is good, how it is

commercially viable etcetera, so yield should be very good.

So, for that if number of levels of metallization increases, so then automatically you have

to compromise with some yield but you have to make a compromise on a good yield. At the

same time, number of wiring level increases that is the motto and target. And mask count

is going to increase if the levels are more. So that the interlevel metal you have to have

a dielectric layer then some metal pattern then again another dielectric layer so automatically

the mask level will also increase. So that was the present scenario.

Now the size what i am discussing does matters how you can see this figure here. So, this

is the the area of the micromachining and this Nano machining. So another word you are

coming across now is machining. So machining, the terminology initially it was in mechanical

engineering, people they used to point machining, that means from a huge bulk steel or any of

the metal beam they used to machine it to get small miniature structures. Well later

on the machining is used in microelectronics laboratory also to fabricate the MEMS devices.

Now here you can see the 1meter, that is that elephant and then is gone down to 0.1 so that

is the chip size is you say this is the area where 0.01 meter to 1 centimeter in that area

you can get the IC chip.

Then this is the size of 1 millimeter the grain of sand and then biological cell comes

nearly 0.01 millimeter to 10 micrometer and then

comes 1 micrometer which is the smallest feature size 0.35 micrometer is sometimes back may

be in 1996,97 where that level is micro. Now, if you go beyond that 0.1 micrometer below,

that is entering to the nano area and there some of the examples are shown that the atomic

littering using the scanning telling microscope. This is

1 nanometer, they are obtained from the feature size then DNA is of the 2 nanometer wide that

is the size.

On the other hand if you see the machining, this is the micro machine gear which is nearly

100 micrometer, then this is dust particle side you can compare with that which is a

1 to 5 micrometer and these are some quantum electronic structures, the width of these

structures in nearly 200 Angstrom and the atomic level 1 to 4 Angstrom. So that means,

the size does matters because the with the reduction of the size and minimum feature

size all the technology is going to change and at the same time the equipments are going

to change and if you go below say 1 nanometer level, then physics of devices is going to

change.

So now, if you look here, the size also on the scale that is bottoms up and here it stops

down. So both are shown, here the few areas are is basically plant and animal cell and

this is the bacteria size is the 1 micrometer to 10 micrometer and 10 to 100 micrometers

are plant and animal cell. This is the area where basically the MEMS

are made and now if you go beyond that, which is not microelectronics that is basically

coming nano scales or nano electronic their size comes below the 100 nanometer to say