Name: 5.2.6 Timing Example
Uploaded: 2020-03-29T16:18:15.000Z
Duration: 3 min 29 s
Description: Thousands of YouTube videos with English-Chinese subtitles! Now you can learn to understand native speakers, expand your vocabulary, and improve your pronunciation...

Using a D register as the memory component

in our sequential logic system works great!

which then appears at the register's output

as the current state for the rest of the clock period.

The combinational logic uses the current state and the value

of the inputs to calculate the next state and the values

A sequence of rising clock edges and inputs

In the next chapter we'll introduce a new abstraction,

finite state machines, that will make it easy to design

Let's use the timing analysis techniques we've learned

on the sequential logic system shown here.

The timing specifications for the register and combinational

Here are the questions we need to answer.

The contamination delay of the combinational logic isn't

What does it have to be in order for the system

Well, we know that the sum of register and logic

than or equal to the hold time of the register.

Using the timing parameters we do know along

that the contamination delay of the logic

What is the minimum value for the clock period tCLK?

The second timing inequality from the previous section

than than the sum of the register and logic propagation

delays plus the setup time of the register.

Using the known values for these parameters

What are the timing constraints for the Input signal

relative to the rising edge of the clock?

The Next State signal is the input to the register

so it has to meet the setup and hold times as shown here.

Now it's pretty easy to figure out when Input has to be stable

before the rising clock edge, i.e., the setup time for Input.

plus the setup time for the register, which

In other words, if the Input signal is stable at least 7ns

before the rising clock edge, then Next State will be stable

at least 2ns before the rising clock edge and hence meet

minus the contamination delay of the logic, which

In other words, if Input is stable at least 1ns

after the rising clock edge, then Next State

will be stable for another 1ns, i.e., a total of 2ns

This meets the specified hold time of the register.

This completes our introduction to sequential logic.

and hence is obeying the timing constraints imposed

So next time you see an ad for a 1.7 GHz processor chip,

you'll know where the “1.7” came from!

Subtitles ListPlay Video

5.2.6 Timing Example

discipline

figure

period

dynamic