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• In the last video we built a JK

• flip-flop that didn't work all that well

• with we use an RC circuit to detect the

• rising edge of the clock but because the

• JK flip-flop toggled so quickly we

• encountered this racing phenomenon where

• we toggle many times for each clock

• pulse and we found it was really

• difficult to fix you know almost

• impossible to fix on the breadboard to

• get that clock pulse to be so short you

• know the pulse that we're generating the

• RC circuits from the rising edge of the

• clock to get that to be so short that

• was only toggle once we found out was it

• almost impossible to to get that working

• for bus the on the breadboard so what

• can we do

• well there's another way to build a JK

• flip-flop and that's this circuit here

• which is called a master-slave JK

• flip-flop and so what you'll see if you

• look at this is you see there to

• essentially 2 SR latches built into

• this, there is one here and then one here and

• you can think of this is having you know

• you're you're set in your reset and this

• case will be the Q compliments and

• this will be the Q output and then over

• here you know this will be the reset and

• the set and this is our Q output in

• our compliments Q. So these are

• two SR latches which you know you can

• look at my previous video on those, but then

• outside of that you have these AND gates

• that are essentially gating the clock

• or gating the SR latches based on the

• clock so for the moment let's, let's

• ignore the feedbacks we'll get to that

• in a minute but if you look at just

• these two inputs of the AND gate the J

• input and the clock or in this case

• the K input and the clock

• basically we're saying is we're saying

• this SR latch is not going to be active

• unless the clock is high

• when the clock is high then you know J

• will pass through and set or K will pass

• through and reset anytime the clock is high

• So this is just sort of like a you know an

• SR latch with an Enable you want to think

• of the clock in that way and then same

• thing if you look at that the slave over

• here and on the salve side you've got an SR

• latch as well, the inputs are

• coming from the master but then instead

• of the clock input coming into the AND

• gates you've got the inverted clock

• input and so the slave is only going to

• be active when the clock is low and so

• the interesting piece of this is that

• you're never going to have a situation

• where both of these SR latches are

• active at the same time because the

• clock is either going to be high which

• case this was active or the clock is

• going to be low which case this one is

• active and so if you want to step this

• this flip-flop you want to get the Q

• output to be high then you know you

• bring J high and then you toggle the

• clock high and low and so with J high

• when the clock goes high then it's going

• to set the first latch and so the Q

• output of that first latch is going to

• go high then when the clock goes low

• that enables the second latch and that Q

• output gets fed through and sets the

• second latch which causes this Q output

• to go high so you can see setting the J

• input toggling the clock high then low

• causes the Q to get set and then the

• same way with K if you set K high and

• then you toggle the clock high then

• low that it resets

• this latch and then the clock goes low

• and reset this latch which resets the

• output so it sets Q to 0 so effectively kind

• of a two-step process with the clock

• has to go high then low now what about

• that JK flip-flop so we should have that

• property where J&K are both high than

• the output should toggle each time the clock

• pulses so in that case when J & K are both

• high when the clock goes high the first

• latch is either going to set or reset

• depending on what the current output is

• so the current output is that Q is high

• then he's gonna come out here and this

• the AND gate is going to turn on its

• going to reset but if the current output

• is low and then a compliment output is

• high then this is going to come around

• at the top AND gate is going to turn on

• its going to set so essentially this

• first latch will output on this Q the

• opposite of whatever currently being

• output over here if both JK are set and

• the clock is high but its fine if the

• clock stays high because the second

• latch is not going to be enabled the

• clock is high then when we invert it this

• is going to be a LOW these AND gates are

• going to be off this latch is not going

• to be active and so this output will

• stay stable so it doesn't matter if the

• clock state high for for whatever period

• of time the first latch will switch but the

• second one won't until the clock goes

• low once the clock goes low then that

• second latch enables and the output of

• the first latch gets fed into the second

• latch so whether that was setting it or

• resetting it and then when that second

• latch either sets or resets that's when

• the final output changes and of course

• at that point the output changes it

• doesn't matter what's getting fed into

• the first stage over here because your

• clock is low at this point and so these AND

• gates you both going to be OFF so

• nothing is going to change here

• So this circuit essentially has the

• exact same behavior as the first circuit

• that we're looking at except we don't

• have this issue of of trying to make

• sure this pulse is so narrow that we

• don't have this racing where you know

• the outlet toggles and then a toggles

• again and toggles again toggles again

• over and over because we're not we're

• not trying to use it on RC circuits to

• create a pulse out of our clock where

• you know using the fact that the clock

• goes high to set one latch and when the

• clock goes low to set the next latch

• based on the first latch in that way our

• feedback you know can't get back around

• to the input until you have a full clock

• cycle and so this way this will only

• toggle once per clock cycle and we don't

• have to deal with any of the you know

• really stringent timing requirements you

• know where we're looking at this you

• know 40 milliseconds propagation time

• and so forth so go ahead built the this

• circuit master-slave JK flip-flop and

• just like last time i've got two inputs

• here this is our J&K input and again

• they're you know tide low to this

• pulldown resistor but then when you push

• the button that goes high. So those

• two inputs go into this is again are

• our three input AND gates so both of the

• input go into those 2 AND gates and

• then this this white wire is connecting

• our clock and so will connect our clock

• into that and then of course with the

• third input is the feedback that comes

• back around that these two green wires

• here and the output of these AND gates are

• the two blue wires to go up to our to

• our first two NOR gates which are the

• top two NOR gates