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  • [MUSIC]

  • As

  • that news article said it has been 25 years since NAND flash

  • memory has been around. So, what I wanted do is give you a 5

  • minute you know, plug-in of what has happened in this 25 year period.

  • So, these memory cells were available before 1984 as well.

  • You, you can program a non-volatile memory.

  • But to erase them, you had to

  • place them under UV light. So these were you had to simply.

  • I don't know if any of you had used these chips.

  • But you had take them under a UV light if you wanted to erase them.

  • Then in 1984 this gentleman Masuoka san, from

  • Toshiba, he invented this flash memory cell, and it was of the NOR architecture.

  • He presented in the IEDM conference that year.

  • Earlier that year, he applied for a patent for the same.

  • And this was you know, the first cell which you could

  • program using electrical signal and also erase it using electrical signal.

  • But this was not a kind of memory.

  • same set, same bunch of characters, they again target you know this weakened

  • increase the density. And they they came up with using this

  • [UNKNOWN]

  • fashion, this was presented in 1988,

  • [UNKNOWN]

  • in the same year. And you can see that

  • [UNKNOWN]

  • it's was, it just the number size of it has gone up but

  • it essentially that same architecture.

  • And Mr. Masuoka's son was actually, instead

  • of being rewarded for his invention, he was

  • he was demoted from his position and that you know, so this is something very

  • particular to Japanese culture. I showed you that the election on

  • [INAUDIBLE]

  • he somewhat resigned from Hitachi.

  • And he too you know, didn't get any benefit for his innovation.

  • And so there was

  • [INAUDIBLE]

  • awarded him a very big award in 2002.

  • But inspite of inventing this multi-billion dollar market.

  • His parent company did not give him any rewarded,

  • [UNKNOWN]

  • a nice article about him. Now, he is a professor at Tohoku.

  • So, I find this you know, very I, I will tell you another story when we get to LED,

  • that was also invented by a Japanese inventor Nakamura San.

  • And he too, was actually demoted because of that invention,

  • and he, he left that company and sued them later.

  • So this is

  • this is something you know, you find very contradictory to the culture in the

  • valley where you are if you are a nail sticking out you get hammered in.

  • If you're in that culture as compared to here, where you,

  • you get rewarded and you can raise money to pursue your idea.

  • But, anyway, the, the next thing which happened was in

  • 1997, people realized that you know, we have this cell,

  • why not start storing more bits into it? So

  • [INAUDIBLE]

  • cell Not really invented, but came in to production in 1997.

  • And most of the cells, that you see in

  • your iPads and in your iPhones are multilevel cell.

  • And then from 2002 to 2010, which is really the post PC era.

  • 2002 it started to just the beginning of it, and since then,

  • the flash memory capacity has doubled every year.

  • So, it's also known as Hwang's Law, and

  • it's a more aggressive law than Moore's law.

  • Moore's law says the capacity should double every 18 months.

  • This law is at your total capacity that you bu, can buy in one chip, not one die,

  • in one chip, should double every year. And in fact, it has been progressing at,

  • at, at least progressed at that rate from 2002 to 2010.

  • It was named after this guy Hwang Chang

  • Gyu, he was a president of Samsung electronics.

  • And Samsung is one of the dominant players in flash memory.

  • Both flash and DRAM memory.

  • Back in 2003, it also also became cheaper than DRAM and it.

  • Nowadays, in most of the memory systems you very limited amount of DRAM.

  • But most

  • of your storage happens in in your nine, and that's

  • because it's, it's an order of magnitude cheaper than DRAM.

  • And 2000, in this year, you can buy, one single die, which has 128

  • gigabit or 16 gigabyte of storage in one single die.

  • You can also buy this tinny chip which stores 120 giga, gigabytes.

  • So most people you know, their hard disk, most of

  • the storage requirement can be met by this one single chip,

  • which has almost the capacity of your hard drive.

  • But still remains much more expensive than hard drive.

  • That's why hard drives have been so hard to displace.

  • And it's still an order of magnitude expensive than hard drives.

  • And that's because hard drives prices also keep on falling.

  • So, I described these numbers, right, that nine flash cost a

  • dollar a giga, a gigabyte, or 70 cents a gigabyte.

  • So.

  • But, I was not describing those numbers for a, a single level cell.

  • But those are for a two bit two bit

  • [UNKNOWN]

  • that's most commonly used in most of your iPhones and iPads.

  • Alright.

  • So, any, any questions on history. Alright.

  • So, let's look at how do we makes these make these chips.

  • Right?

  • So let's look at the process technology. It's of course about manufacturing, so.

  • So this is how, if you open one of these chips

  • up, it would look like you see these these break lines.

  • And they'll be separated by these very high aspect ratio trenches.

  • So a quick question to answer that you know, we have learned about lithography.

  • So looking at this picture.

  • what do you think, which lithography was used?

  • If you look a, a little deeper and you think about it, you see these two

  • different trench depths.

  • So clearly you know it looks like the use double patterning technique.

  • And this is not a chip from 2012.

  • It's actually a chip from 2007.

  • And for flash memory has been using double patterning

  • for a while, before even logic started using it.

  • So, if you open up your iPhone as we did in our first task, you see that

  • this big chip that is your nine memory chip.

  • And whether you buy 16 gig phone or you buy 32

  • or 64 gig phone, you always get that one single chip.

  • So why, how is that possible?

  • Right?

  • So the reason why it's possible is that, if you open up that chip, it's

  • not just one die but it's multiple of these dies stacked on top of each other.

  • So, you can have up to 32 of these dies stacked on top of each other.

  • Each of these would be eight gigabyte or somewhere in that order.

  • And there you know, they are still connected using these wire bonds.

  • And we'll talk about, when we talk about when we discuss

  • packaging in in lecture number six that how these are connected together.

  • And it is quite amazing, that you know, that 32 of these chips and you have these

  • wire bonds and none of them sharp to each other.

  • And if you look at each one of this

  • die, it's essentially nothing but a large area of memory.

  • And often memory are divide, is defined by this term, which is called array

  • efficiency, that is, how much die area is covered with the actual memory cell.

  • So, a DRAM, for example, has an area efficiency of 60%.

  • nine flash has area efficiency of 90 to 80%,

  • that is more than 80% of this dye is just this die is just this nine

  • [INAUDIBLE].

  • The rest, the 20% of this peripheral circuit circuitry, your

  • charge pumps that would be required to generate that high voltage.

  • And your row and page decoders, but still 80%

  • of the area, it's nothing but these banks of memory.

  • Right?

  • So, how do we make these things? I

  • [UNKNOWN]

  • for that, it

  • for making this a pretty simple device, what you need

  • to do is pattern bit lines, and then pattern word lines.

  • And for each of these intersections, you get a cell below them.

  • Right?

  • So let's look at some of these intersections.

  • So when you pattern these bit lines, you

  • essentially separate them with a shadow trench isolation.

  • Each of them is guiding such a high voltage,

  • you isolate them so that the way deep STI

  • edge to separate them. And when you draw these word lines, these

  • board lines we'll these, they tend to overlap and flow around this bit lines.

  • And I'll show you why that is the case.

  • So, let's look at a few of these little cross sections.

  • This cross section I already showed you.

  • This is a cross section taken along this direction.

  • So, if you have the multiple bit lines and if you take a cross

  • section like this, what do see is these bit lines

  • and they're separated by this very high aspect ratio STI etch.

  • So this is a very sophisticated, not sophisticated but a

  • very high aspect ratio structure that you need to etch.

  • Then you also need to fill it, and that's what separates these different bit lines.

  • And on

  • top of these bit lines, you can see a cell over

  • here that this this is your, where your cell is located.

  • Right?

  • Now, what if we looked a cross section along this site?

  • So if you take a cross section along your, along one

  • of your bit line, that is intersecting multiple of these word lines.

  • What you see in this cartoon

  • is essentially these multiple of these transistors.

  • Right?

  • Or multiples of these apartments, which are connected in series to each other.

  • Right? Or, if you draw if

  • you draw

  • a more device friendly kind of picture,

  • you see these multiple of these gate stacks.

  • And these transistors connected in series to each other.

  • Right?

  • So this is a actual picture which I showed you earlier other side shows.

  • This is a picture taken along one of these

  • word lines, so you see multiple of these transistors.

  • And at the end, you have something connecting,

  • but in between them essentially, it's just a string of

  • transistors and they are just connected in series to each other.

  • And to read anyone of them, I need to turn

  • on all these others so I can read what's in here.

  • Right?

  • So let's look at, a closer look at how it

  • looks like when I look along a vertical word line.

  • So when I look along a vertical word line,

  • this word line is wrapping around my different bit lines.

  • And you can clearly see over here, so this is the

  • [INAUDIBLE]

  • of one of the STI etches.

  • And I have my tunnel oxide over here, and this tall thing is my floating gate.

  • But what I see as my word line, or my control gate, is wrapping around it.

  • So I see this

  • [UNKNOWN]

  • this is my interparty dielectric.

  • And this other whole thing on the top

  • which is wrapping around is my control gate.

  • So the reason why it's wrapped around is because you want to, remember

  • our GCR which I said, we want to keep it as high as possible.

  • So we want to keep this word line

  • capacitance with my cell as high as possible.

  • And one way to increase that capacitance is

  • this wrap around that contact around my gate.

  • Right?

  • So I get more area and I get more

  • capacitance, and that's how people have been doing it.

  • So this word line wrapping around your cell is to essentially

  • achieve a high gate coupling ratio. So now you can see 1,

  • 2, 3, 4 of these STIs standing out.

  • And then you have your tunnel oxide over here.

  • This is your floating gate.

  • And then you can see you this n or n dielectric RER control gate on top of

  • that dielectric wrapping on on top of these cells.

  • Any questions on this one?

  • So

  • actually this

  • [INAUDIBLE]

  • has accelerated this flash memory so much

  • that it, you know, it has developed far beyond what people predicted it to.

  • It has scaled far beyond what people expected to happen.

  • So this a picture from the ITRS road map of 2006.

  • And it says that you

  • know, in 2012, we'll have a memory available with 32 nanometer feature sign.

  • And was circled in red, so people didn't know how it will happen.

  • Right? It was so uncertain back in 2006.

  • But since economy drove it. Since the, iPhone, iPads drove it so much,

  • actually this happened much before. In 2000 12, you can buy a chip which is 20

  • nanometer in feature size and 64 gigabit in one single die.

  • So it's, you know it's hard to predict the future.

  • And so it's all driven by so this is how aggressive your

  • [UNKNOWN]

  • device that have driven the flash memory.

  • Right?

  • And since it's a very simple layout, I showed you a layout

  • that's essentially nothing but these very periodic bit lines and word lines.

  • So it's a very simple structure to write lithography on.

  • There's no grating, I mean, no, there's no cut required.

  • All that's required is these gratings.

  • so this in fact has

  • become the driver for lithography as well, so NAND

  • flash was the first to use our double patterning.

  • It has been using it for a quite a few generation now, and

  • it's right now they are the first to use quadruple patterning as well.