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  • Welcome to the Creator's Comments!

  • Thanks for taking interest in reading the comments.

  • They aren't really timed to the audio, but will be spaced 4sec apart.

  • To start, this video takes the #1 position for the most script revisions.

  • By the end, I was at revision 40 of the script, just because it was such

  • a complex topic that needed, and needed a good amount of scaffolding.

  • A lot of complex details were cut out, so it's a good thing you're here reading

  • the creator comments because we'll get to every detail that got cut from 39 revisions of script writing.

  • Also this was the first script where I included a sponsor, so I hope you didn't

  • mind the sponsored segments much. I tried to make them educational and integrated into the content.

  • So one confusing detail is that transistors usually operate under one set

  • of ON/OFF conditions, in order to perform MOSFET logic. Whereas

  • these memory cells have three operational states, 1) Writing to a cell

  • 2) Reading from a cell, and 3) Erasing a cell.

  • So, 95% of THIS video is about reading from a cell.

  • Versus the previous video on quantum tunneling is 95% about writing to a cell.

  • Don't mix up the operational modes of writing vs reading from a cell.

  • I'll get to erasing a cell in a future episode. But that video will be in a slightly different format.

  • So: I might as well lay this out here: 1 bit per cell = Single Level Cell [SLC]

  • 2 Bits Per Cell = Multi Level Cell [MLC] 3 Bits Per Cell = Triple Level Cell [TLC]

  • 4 Bits Per Cell = Quad Level Cell [QLC]

  • Quad level cells are more cutting edge, however there is a huge trade-off.

  • With QLC you can fit more bits, but 1) it takes a little longer to read information.

  • 2) It takes a TON of time longer to write information to each cell

  • 3) The threshold voltages are a lot closer so there is a

  • higher liklihood of the data becoming corrupt more quickly.

  • So TLC charge trap flash is the most common type of memory cell.

  • Moving on, his enterprise SSD has 18 chips, and in each chip there are 8 or 16 die.

  • One die is the layout of charge trap flash cells that we showed earlier and will show in a few seconds.

  • FYI- there are 300 pints in this board to board connector... I counted...

  • 30 x 10... I didn't count every pin- that would be silly.

  • Furthermore, in that SSD there are a set of DRAM and a pretty powerful controller.

  • I say 100's of millions here, because there is a wide range storage capacities

  • from smartphone to smartphone. This layout is for a single 1TB chip

  • that is stacked 16 chips tall. But if you have a phone with a smaller capacity

  • then the # of cells in each die is in the 100s of millions range.

  • The calculations aren't that difficult overall, but the issue comes down

  • to the variation in height, width, and depth of the die,

  • how many die are in each microchip, and then how many microchips are

  • in the particular SSD. But overall it should be closer to

  • 170-200ish billion memory cell range for a 64 GB single chip.

  • Let's move on and briefly talk about this structure

  • First, this structure isn't hollow but rather the empty areas are surrounded by insulating material.

  • The indent of the charge trap helps to prevent charges from leaking from one celll

  • to the cell above it. Furthermore the charge trap is composed of silicon nitride

  • which is a dielectric itself, and is not conductive to having charges flow.

  • The main difference between floating gate transistors and charge trap [CT] transistors

  • IS in fact the fact that in [CT] transistors the charge trap is a dielectric material.

  • The channel is a lightly n-doped polysilicon.

  • The core filler is also a high K- dielectric.

  • The core filler is actually critical because by using it, the channel becomes

  • a hollow cylinder, or a 'macaroni' shape. This makes it such that the charge trap and gate

  • have a stronger influence, and better control of the the channel

  • Also 'macaroni' shape is the technical word I found in the textbooks.

  • Okay, so for the next few minutes I'm gonna discuss a pretty significant

  • "inaccuracy" I told throughout this entire episode.

  • The inaccuracy is that the charge trap flash memory cell operates

  • more like a depletion-mode N-Channel MOSFET.

  • And what I'm describing here is an enhancement-mode N-Channel MOSFET.

  • If you don't know the difference, then you don't have to worry, but I'll explain it anyways.

  • In essence, in a charge trap transistor, and in depletion mode mosfets, the channel is

  • ON when 0V is applied to the gate.

  • In this graph I don't have numbers along the axis, but,

  • if the 0V line were in the middle of the ON side, then this graph would be

  • accurate, and when a negative volt is applied to the gate, the channel turns off.

  • So why did I use this inaccuracy as the example? Well, the most common

  • transistor is an Enhancement Mode N channel MOSFET, and the target audience

  • for this video are high school students who may know what a transistor is, but

  • for certain have no clue about enhancement mode vs depletion mode

  • and have no clue about P vs N channels mosfets. So I stuck with the most

  • common mosfet as the starting point, which is the N-Channel Enhancement

  • MOSFET. And along that point, going into explaining ohmic regions vs. saturation

  • regions would be even more confusing. If you want to learn more about that get an EE degree.

  • BUT, if I were to talk about this charge trap transistor accurately, the lesson

  • would go something like this:

  • Normally, electrons CAN flow through the channel.

  • When 0V are applied to the gate, and there are no charges on the

  • charge trap, electrons can flow through the channel.

  • But, when electrons are added onto the charge trap, these electrons

  • inhibit the flow of electrons through the channel.

  • However, when a positive voltage is applied to the gate, this voltage

  • negates the negative charges on the charge trap,

  • thus allowing the electrons to be able to flow through the channel again.

  • And when even more electrons are added to the charge trap

  • that means an even larger positive voltage on the gate is required

  • to negate the negative charges on the charge trap.

  • That's it. This would have been an equally useful and thorough

  • explaination, however, it would confuse viewers who have learned about

  • the basic mosfet, which is normally OFF when 0V is applied to the gate.

  • And this lesson would have less of a lesson around threshold voltages.

  • Okay, so lets get to specific voltages.

  • In this setup, of a single level cell without any charges on the CT,

  • the threshold voltage is somewhere around -0.5V.

  • When electrons are placed on the CT, the threshold voltage shifts to around 3V.

  • In order to write to a memory cell, in essence pulling charges

  • from the channel into the CT, around 18-20V is required on the gate.

  • Which is a LOT higher voltage than when just reading information.

  • Furthermore, when you write to a cell, first you try to pull the charges

  • through the tunnel oxide with 19ish V. And then you verify the stored number

  • of electrons by applying the two separate threshold voltages.

  • But when we get to TLC, or three bits of information, the writing voltage

  • stays the same, but the threshold voltages are divided up from 0-4.5ish V.

  • Similarly, after every step of writing to a memory cell, each memory cell's value

  • for that attempted writing step is verified. It's easier to show with a graph

  • which I'll do in a future episode.

  • Another key detail is that the gates between all the memory cells in

  • a page are connected to one another, and a page is 40,000ish memory cells.

  • So when writing or reading to a cell, all 40,000 memory cells undergo the

  • same operation. [Side note, when erasing, and entire block is erased]

  • However this poses a problem- how is a single charge trap prevented from

  • being written to, or specifically prevented from having electrons

  • tunneled through the oxide from the channel and into the charge trap?

  • Well, to prevent writing, the channel is biased to around 8V. And this

  • makes the gate to channel potential only 12V, which isn't strong enough to

  • tunnel the electrons. So as an example, when writing to a cell, the Gate is

  • driven to 18V for a ~100 microseconds. If a memory cell doesn't want its charge

  • trap to have electrons on it, the channel of that memory cell is biased to 8 V.

  • Next, the gate voltage is dropped to 0V, and each channel is checked whether

  • its on or off to verify that the electrons moved as expected onto the appropriate

  • charge traps. Next, the voltage is set to 18.3V, and again, the cells that don't want

  • to be changed have their channel biased to 8V. And then the voltage

  • is dropped down to the corresponding expected threshold voltage.

  • And this process repeats over and over, until each memory cell has the

  • desired number of electrons set into the charge trap. This is a long process, and

  • is even longer when dealing with QLC, or quad level cells.

  • So onto the inverted assignment, and why no electrons is a 0, and some electrons

  • are a 1. I asked a few scientists and engineers this, and they replied that it was

  • with this generation of technology, it is mostly arbitrary. In fact, for TLC the

  • assignment from lowest threshold voltage to highest threshold voltage

  • goes 111, 011, 001, 101, 100, 000, 010, 110. With 111 = Erased and

  • 110 = the most electrons in the charge trap.

  • The order of 111, 011, 001... follows a gray code where each subsequent

  • value has only 1 bit changed, however there are a lot of different ways

  • this grey code could be ordered, and with that different companies follow

  • different binary schemes. The purpose of the grey code is to help improve

  • reliability, and error checking.

  • But overall it doesn't have to be a specific order. Or at least that's what

  • I found in my research.

  • One interesting detail about these enterprise SSDs, is that they

  • have a DWPD spec, which stands for daily writes per day.

  • The 'Enterprise Write Intensive SSD' can have capacities up to 3.2TB, and

  • have 10 DWPD, with a warranty of 5 years.

  • That means that for 5 straight years, this SSD can be writing and replacing

  • its 3.2 TB of information, 10 times a day.

  • That's about 58.4 Petabytes of data written and erased over 5 years!

  • I know these SSDs are used for transactional data, but that's just

  • a ton of write / erase cycles for a single SSD to perform.

  • Another detail not entirely discussed in this episode is that the data

  • written to and read from a single SSD is distributed relatively evenly throughout

  • all the chips and die on that SSD. To explain that better. As mentioned before,

  • In that KIOXIA enterprise SSD there were 18 chips, and in each chip theres

  • a stack of lets say 8 die [approx] , or 8 layouts like the massive layout we are showing.

  • When you take a video, that video is broken up and evenly distributed across

  • those 144 [8x18] die. You would think that the entire video should be

  • stored on a single die, but in order to erase/ write and read significantly faster, the

  • single file is chopped up into block size pieces and stored across all of the die.

  • As mentioned before, in a single die, only one page can be written to or read

  • at any given time. But when the data gets written to or read from 144 die,

  • that means there are 144 pages written to or read from simultaneously.

  • That being said, a small portion of each die is assigned to error correcting code

  • so that if any of the die has a failure, then none

  • of the data is lost. In fact these enterprise SSDs have a spec

  • that say 2 of the entire chips can undergo failures, and all your data

  • will still maintain its full integrity. That's actually why there are 18 chips

  • instead of 16 [where 16 is a power of 2, and a lot of things in computers

  • are found in powers of 2].

  • Moving on- just to quickly repeat in case someone joined these creators

  • comments a little bit late. The order of binary assignment to threshold voltages

  • of 111, 110, 101, 100, 011, 010, 001, 000, where 111 is no electrons

  • is inaccurate. It should be 111, 011, 001, 101, 100, 000, 010, 110 as an example.

  • But this assignment would be hella confusing for most people, and it would

  • open up a set of additional questions that I couldn't really dive into in this episode.

  • Also, as for the specs listed above, there are a wide range of different

  • specs for SSDs in terms of capacity, price, read and write speeds,

  • reliability, daily writes per day, power consumption, form factor.

  • In general, enterprise SSDs cost more, and have higher read write speeds, and

  • better reliability. Also another question is, if SSDs have a 5 year warranty [typically]

  • why would anyone ever get a 30TB SSD? Especially considering 30TB

  • would usually be used for long term storage. The answer is that there are

  • a good number of applications, specifically in research, simulation, or

  • transactions, that require incredible amounts of storage space,

  • but don't use that storage space in the form of static long term files.

  • As for dimensions, the entire cell is somewhere in the range of

  • 160 - 200 nanometers wide. However I don't have exact numbers as these are

  • very closely held secrets. On each side, the dielectric between the

  • control gate and charge trap is around 15 nm. The charge trap of Silicon nitride

  • is 50ish nanometers, the tunnel oxide is 8 nanometers, and then the channel

  • is around 10ish nanometers. Maybe one day I'll work with a company

  • who shares revealing more details, but until then I just gotta go from what

  • I can find in text books.

  • Anywho, thanks a ton for reading these creator's comments

  • If you have any further question post them in the comments below!!

  • Also, as mentioned in a previous episodes creator comments

  • this technology is not designed and created by aliens, there is a long list of

  • companies and progressive developments throughout the past 70 years.

  • Also if aliens did give us this technology

  • why didn't they also give us the technology to create

  • giant Jaegers [giant robots].

Welcome to the Creator's Comments!

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B1 US trap charge voltage channel gate threshold

How does NAND Flash Work? Reading from TLC : Triple Level Cells || Exploring Solid State Drives

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    OolongCha posted on 2021/04/08
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